HD6432670 Hitachi, HD6432670 Datasheet - Page 445

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

9.3
The DTC operates when activated by an interrupt or by a write to DTVECR by software. An
interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER
bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the
activation source or corresponding DTCER bit is cleared. The activation source flag, in the case
of RXI0, for example, is the RDRF flag of SCI_0.
When an interrupt has been designated a DTC activation source, existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC operates in accordance with the default priorities.
Figure 9.2 shows a block diagram of activation source control. For details see section 5, Interrupt
Controller.
9.4
Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF).
Register information should be located at the address that is multiple of four within the range.
Locating the register information in address space is shown in figure 9.3. Locate the MRA, SAR,
MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register
information. In the case of chain transfer, register information should be located in consecutive
areas as shown in figure 9.3 and the register information start address should be located at the
corresponding vector address to the activation source. The DTC reads the start address of the
register information from the vector address set for each activation source, and then reads the
register information from that start address.
Activation Sources
Location of Register Information and DTC Vector Table
Source flag cleared
IRQ interrupt
supporting
DTVECR
On-chip
module
Figure 9.2 Block Diagram of DTC Activation Source Control
Interrupt
request
DTCER
Select
Clear
Interrupt controller
controller
Clear
DTC
Clear request
Interrupt mask
Rev. 2.0, 04/02, page 399 of 906
CPU