HD6432670 Hitachi, HD6432670 Datasheet - Page 538
HD6432670
Manufacturer Part Number
HD6432670
Description
(HD64F267x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432670.pdf
(953 pages)
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10.15.1 Port G Data Direction Register (PGDDR)
The individual bits of PGDDR specify input or output for the pins of port G.
PGDDR cannot be read; if it is, an undefined value will be read.
Bit
7
6
5
4
3
2
1
0
Notes: 1. PG0DDR is initialized to 1 in modes 1, 2, 5, and 6, and to 0 in modes 3, 4, and 7.
Rev. 2.0, 04/02, page 492 of 906
Bit Name
—
PG6DDR
PG5DDR
PG4DDR
PG3DDR
PG2DDR
PG1DDR
PG0DDR
2. Only in H8S/2678R Series.
Initial Value
0
0
0
0
0
0
0
1/0*
1
R/W
—
W
W
W
W
W
W
W
Description
Reserved
If read, it returns an undefined value.
Pins PG6 to PG4 function as bus control input/output
pins (
appropriate bus controller settings are made.
Otherwise, these pins are I/O ports, and their
functions can be switched with PGDDR.
When the
set to 1, pins PG3 to PG0 function as
when the corresponding PGDDR bit is set to 1, and
as input ports when the bit is cleared to 0. When
CS3E to CS0E are cleared to 0, pins PG3 to PG0 are
I/O ports, and their functions can be switched with
PGDDR.
Pins PG6 to PG4 function as bus control input/output
pins (
appropriate bus controller settings are made.
Otherwise, these pins are output ports when the
corresponding PGDDR bit is set to 1, and as input
ports when the bit is cleared to 0.
When the
set to 1, pins PG3 to PG0 function as
when the corresponding PGDDR bit is set to 1, and
as input ports when the bit is cleared to 0. When
CS3E to CS0E are cleared to 0, pins PG3 to PG0 are
I/O ports, and their functions can be switched with
PGDDR.
Pins PG6 to PG0 are I/O ports, and their functions
can be switched with PGDDR.
Modes 1, 2, 4, 5, and 6
Modes 3*
Modes 3*
2
2
,
,
, 7 (when EXPE = 1)
, 7 (when EXPE = 0)
output enable bits (CS3E to CS0E) are
output enable bits (CS3E to CS0E) are
, and
, and
) when the
) when the
output pins
output pins
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