HD6432670 Hitachi, HD6432670 Datasheet - Page 405

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

When transfer is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the DMA
transfer period. In block transfer mode, since a block-size transfer is carried out without
interruption, the EDA bit remains at 1 from the time 0 is written to it until the end of the current
block-size transfer.
In burst mode, transfer is halted for up to three DMA transfers following the bus cycle in which 0
is written to the EDA bit. The EDA bit remains set to 1 from the time of the 0-write until the end
of the last DMA cycle.
Writes (except to the EDA bit) are prohibited to registers of a channel for which the EDA bit is set
to 1. When changing register settings after a 0-write to the EDA bit, it is necessary to confirm that
the EDA bit has been cleared to 0.
Figure 8.12 shows the procedure for changing register settings in an operating channel.
BEF Bit in EDMDR: In block transfer mode, the specified number of transfers (equivalent to the
block size) is performed in response to a single transfer request. To ensure that the correct number
When an NMI interrupt is generated, and transfer halts
A reset
Hardware standby mode
When 0 is written to the EDA bit, and transfer halts
Changing register settings
Figure 8.12 Procedure for Changing Register Settings in Operating Channel
Change register settings
changes completed
in operating channel
Write 0 to EDA bit
Register setting
Read EDA bit
EDA bit = 0?
Yes
No
1
2
3
4
1. Write 0 to the EDA bit in EDMDR.
2. Read the EDA bit.
3. Confirm that EDA = 0. If EDA = 1, this
4. Write the required set values to the
indicates that DMA transfer is in progress.
registers.
Rev. 2.0, 04/02, page 359 of 906