HD6432670 Hitachi, HD6432670 Datasheet - Page 735

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Data transfer with the types of IC cards (direct convention and inverse convention) are performed
as described in the following.
As in the above sample start character, with the direct convention type, the logic 1 level
corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order.
The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV
bits in SCMR to 0. According to the Smart Card regulations, clear the O/
select even parity mode.
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to
state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. For
the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to the Smart
Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z.
In this LSI, the SINV bit inverts only data bits D7 to D0. Therefore, set the O/
to invert the parity bit for both transmission and reception.
When there is no parity error
When a parity error occurs
Legend
Ds
D0 to D7
Dp
DE
(Z)
(Z)
Figure 15.24 Inverse Convention (SDIR = SINV = O/
Figure 15.23 Direct Convention (SDIR = SINV = O/
Figure 15.22 Normal Smart Card Interface Data Format
: Start bit
: Data bits
: Parity bit
: Error signal
Ds
Ds
Ds
Ds
A
A
D0
D0
D7
D0
Z
Z
D1
D1
D6
D1
Z
Z
Transmitting station output
Transmitting station output
D5
D2
D2
D2
A
A
D4
D3
A
Z
D3
D3
D3
D4
A
Z
D4
D4
D2
D5
A
Z
D5
D5
D1
D6
A
A
D6
D6
D0
D7
A
A
Dp
Dp
D7
D7
Z
Z
Rev. 2.0, 04/02, page 689 of 906
Dp
Dp
(Z)
(Z)
Receiving station
output
bit in SMR to 0 to
State
State
= 0)
= 1)
DE
bit in SMR to 1