HD6432670 Hitachi, HD6432670 Datasheet - Page 810

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

19.8.2
When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.11 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
5. For a dummy write to a verify address, write 1-byte data H’FF to an address whose lower two
6. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as
19.8.3
All interrupts, including NMI input, are disabled when flash memory is being programmed or
erased, and while the boot program is executing in boot mode. There are three reasons for this:
1. Interrupt during programming or erasing might cause a violation of the programming or
2. If the interrupt exception handling is started when the vector address has not been programmed
3. If an interrupt occurred during boot program execution, it would not be possible to execute the
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registers (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn.
Set a value greater than (y + z +
bits are B’00. Verify data can be read in longwords from the address to which a dummy write
was performed.
before. The maximum number of repetitions of the erase/erase-verify sequence (N) must not
be exceeded.
erasing algorithm, with the result that normal operation could not be assured.
yet or the flash memory is being programmed or erased, the vector would not be read correctly,
possibly resulting in CPU runaway.
normal boot mode sequence.
Erase/Erase-Verify
Interrupt Handling when Programming/Erasing Flash Memory
+ ) ms as the WDT overflow period.