HD6432670 Hitachi, HD6432670 Datasheet - Page 201
HD6432670
Manufacturer Part Number
HD6432670
Description
(HD64F267x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432670.pdf
(953 pages)
- Current page: 201 of 953
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Only the basic bus interface can be used for area 6.
Area 7: Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode,
the space excluding the on-chip RAM and internal I/O registers is external address space. The on-
chip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when
the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in
external address space.
When area 7 external address space is accessed, the &6 signal can be output.
Only the basic bus interface can be used for the area 7 memory interface.
6.4.4
Chip Select Signals
This LSI can output chip select signals ( &6 to &6 ) for areas 0 to 7. The signal outputs low when
the corresponding external space area is accessed. Figure 6.7 shows an example of &6 to &6
signals output timing.
Enabling or disabling of &6 to &6 signals output is set by the data direction register (DDR) bit
for the port corresponding to the &6 to &6 pins.
In expanded mode with on-chip ROM disabled, the &6 pin is placed in the output state after a
reset. Pins &6 to &6 are placed in the input state after a reset and so the corresponding DDR bits
should be set to 1 when outputting signals &6 to &6 .
In expanded mode with on-chip ROM enabled, pins &6 to &6 are all placed in the input state
after a reset and so the corresponding DDR bits should be set to 1 when outputting signals &6 to
&6 .
When areas 2 to 5 are designated as DRAM space, outputs &6 to &6 are used as 5$6 signals.
When areas 2 to 5 are designated as continuous synchronous DRAM space in the H8S/2678R
Series, outputs &6 , &6 , &6 , and &6 are used as 5$6 , &$6 , :( , and CLK signals.
Rev. 2.0, 04/02, page 155 of 906
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