HD6432670 Hitachi, HD6432670 Datasheet - Page 324

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit
2
1
0
Rev. 2.0, 04/02, page 278 of 906
Bit Name
DTIE1A
DTIE0B
DTIE0A
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Data Transfer End Interrupt Enable 1A
Enables or disables an interrupt to the CPU or
DTC when transfer ends. If the DTE1 bit is
cleared to 0 when DTIE1A= 1, the DMAC
regards this as indicating the end of a transfer,
and issues a transfer end interrupt request to
the CPU or DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE1A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE1 bit to 1.
Data Transfer Interrupt Enable 0B
Enables or disables an interrupt to the CPU or
DTC when transfer on channel 1 is interrupted.
If the DTME0 bit is cleared to 0 when DTIE0B=
1, the DMAC regards this as indicating a break
in the transfer, and issues a transfer break
interrupt request to the CPU or DTC.
A transfer break interrupt can be canceled
either by clearing the DTIE0B bit to 0 in the
interrupt handling routine, or by performing
processing to continue transfer by setting the
DTME0 bit to 1.
Data Transfer End Interrupt Enable 0A
Enables or disables an interrupt to the CPU or
DTC when transfer ends. If the DTE0 bit is
cleared to 0 when DTIE0A = 1, the DMAC
regards this as indicating the end of a transfer,
and issues a transfer end interrupt request to
the CPU or DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE0A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE0 bit to 1.