HD6432670 Hitachi, HD6432670 Datasheet - Page 182

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.3.8
DRAMCR is used to make DRAM/synchronous DRAM* interface settings.
Note: The synchronous DRAM interface is not supported in the H8S/2678 Series.
Bit
15
14
13
Rev. 2.0, 04/02, page 136 of 906
Bit Name
OEE
RAST
DRAM Control Register (DRAMCR)
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
2(
The OE signal used when EDO page mode
DRAM is connected can be output from the
(OE) pin. The
designated as DRAM space.
When the synchronous DRAM is connected, the
CKE signal can be output from the (OE) pin.
The CKE signal is common to the continuous
synchronous DRAM space.
0:
(
1:
5$6
Selects whether, in DRAM access, the
signal is asserted from the start of the T
(rising edge of ø) or from the falling edge of ø.
Figure 6.4 shows the relationship between the
RAST bit setting and the
The setting of this bit applies to all areas
designated as DRAM space.
0:
cycle
1:
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
2(
2(
2(
5$6
5$6
Output Enable
)/(CKE) pin can be used as I/O port
Assertion Timing Select
/CKE signal output disabled
/CKE signal output enabled
is asserted from ø falling edge in T
is asserted from start of T
2(
signal is common to all areas
5$6
assertion timing.
r
cycle
5$6
r
cycle
r