HD6432670 Hitachi, HD6432670 Datasheet - Page 723

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

No
No
No
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1)
Read ORER and FER flags in SSR
Read ORER and FER flags in SSR
Read receive data in RDR
Read receive data in RDR
Set MPIE bit in SCR to 1
Read RDRF flag in SSR
Read RDRF flag in SSR
Clear RE bit in SCR to 0
FER
FER
All data received?
Start of reception
This station's ID?
Initialization
RDRF = 1?
RDRF = 1?
<End>
ORER = 1?
ORER = 1?
Yes
Yes
Yes
Yes
No
No
Yes
No
Yes
[4]
[3]
[1]
[2]
Error handling
(Continued on
next page)
[5]
[1]
[2]
[3]
[4]
[5]
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
ID reception cycle:
Set the MPIE bit in SCR to 1.
SCI status check, ID reception
and comparison:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
compare it with this station’s ID.
If the data is not this station’s ID,
set the MPIE bit to 1 again, and
clear the RDRF flag to 0.
If the data is this station’s ID,
clear the RDRF flag to 0.
SCI status check and data
reception:
Read SSR and check that the
RDRF flag is set to 1, then read
the data in RDR.
Receive error handling and break
detection:
If a receive error occurs, read the
ORER and FER flags in SSR to
identify the error. After
performing the appropriate error
handling, ensure that the ORER
and FER flags are both cleared
to 0.
Reception cannot be resumed if
either of these flags is set to 1.
In the case of a framing error, a
break can be detected by reading
the RxD pin value.
Rev. 2.0, 04/02, page 677 of 906