HD6432670 Hitachi, HD6432670 Datasheet - Page 560

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Table 11.11 MD3 to MD0
Bit 3
MD3*
0
1
Legend: x: Don’t care
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
11.3.3
TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for
channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected
by the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
Rev. 2.0, 04/02, page 514 of 906
1
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
Timer I/O Control Register (TIOR)
Bit 2
MD2*
0
1
x
be written to MD2.
2
Bit 1
MD1
0
1
0
1
x
Bit 0
MD0
0
1
0
1
0
1
0
1
x
Description
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
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