HD6432670 Hitachi, HD6432670 Datasheet - Page 329

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a
DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA
transfer. With ADI, TXI and RXI interrupts, however, the interrupt source flag is not cleared
unless the relevant register is accessed in a DMA transfer. If the same interrupt is used as an
activation source for more than one channel, the interrupt request flag is cleared when the highest-
priority channel is activated. Transfer requests for other channels are held pending in the DMAC,
and activation is carried out in order of priority.
When DTE = 0 after completion of a transfer, an interrupt request from the selected activation
source is not sent to the DMAC, regardless of the DTA bit setting. In this case, the relevant
interrupt request is sent to the CPU or DTC.
When an interrupt request signal for DMAC activation is also used for an interrupt request to the
CPU or DTC activation (DTA = 0), the interrupt request flag is not cleared by the DMAC.
7.4.2
If an external request (
should be set to input mode in advance. Level sensing or edge sensing can be used for external
requests.
External request operation in normal mode of short address mode or full address mode is
described below.
When edge sensing is selected, a byte or word is transferred each time a high-to-low transition is
detected on the
before data transfer is completed.
When level sensing is selected, the DMAC stands by for a transfer request while the
held high. While the
released each time a byte or word is transferred. If the
transfer, the transfer is interrupted and the DMAC stands by for a transfer request.
7.4.3
Auto-request is activated by register setting only, and transfer continues to the end. With auto-
request activation, cycle steal mode or burst mode can be selected.
In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is
transferred. DMA and CPU cycles are usually repeated alternately. In burst mode, the DMAC
keeps possession of the bus until the end of the transfer so that transfer is performed continuously.
Activation by External Request
Activation by Auto-Request
pin. The next data transfer may not be performed if the next edge is input
pin is held low, transfers continue in succession, with the bus being
pin) is specified as a DMAC activation source, the relevant port
pin goes high in the middle of a
Rev. 2.0, 04/02, page 283 of 906
pin is