HD6432670 Hitachi, HD6432670 Datasheet - Page 412

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and
pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after
the end of the write cycle, and
of operations is repeated until the end of the transfer.
transfer activated by the
Rev. 2.0, 04/02, page 366 of 906
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle start;
[4], [7] When
Address bus
DMA control
Channel
ø
Figure 8.19 Example of Block Transfer Mode Transfer Activated by
Acceptance after transfer enabling;
(As in [1],
pin sampling is performed in each cycle starting at the next rise of ø after the end of the
Pin Low Level Activation Timing: Figure 8.20 shows an example of normal mode
Idle
[1]
Minimum 3 cycles
Request
Bus release
pin high level has been sampled, acceptance is resumed after completion of dead cycle.
pin low level is sampled at rise of ø, and request is held.)
[2]
pin high level sampling is started at rise of ø.
Read
Request clearance period
[3]
Transfer source
DMA read
pin low level.
pin high level sampling for edge sensing is started. If
One block transfer
Write
pin low level sampling is performed again; this sequence
DMA write
pin while acceptance via the
destination
Transfer
pin low level is sampled at rise of ø, and request is held.
Edge
Acceptance
resumed
Idle
[4]
Minimum 3 cycles
Request
Bus release
[5]
Request clearance period
Read
[6]
Transfer source
DMA read
One block transfer
Write
DMA write Bus release
destination
Transfer
pin is possible,
Acceptance
resumed
Idle
Pin Falling
[7]