HD6432670 Hitachi, HD6432670 Datasheet - Page 271

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

(2) Read Data Extension
If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is read-
accessed in DMAC/EXDMAC single address mode, the establishment time for the read data can
be extended by clock suspend mode. The number of states for insertion of the read data extension
cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set the OEE bit to 1 in
DRAMCR when the read data will be extended. The extension of the read data is not in
accordance with the bits DDS and EDDS.
Figure 6.62 shows the timing chart when the read data is extended by two cycles.
Figure 6.62 Example of Timing when the Read Data is Extended by Two States
(DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2)
Precharge-sel
DQMU, DQML
Address bus
or
SDRAMø
Data bus
CKE
ø
PALL ACTV
address
Column
T
p
address
address
Row
Row
T
r
READ
T
c1
T
cl
NOP
T
c2
Column address
Rev. 2.0, 04/02, page 225 of 906
T
sp1
T
sp2