HD6432670 Hitachi, HD6432670 Datasheet - Page 223

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

If a row address hold time or read access time is necessary, making a setting in bits RCD1 and
RCD0 in DRACCR allows from one to three T
to be inserted between the T
the column address is output. Use the setting that gives the optimum row address signal hold time
relative to the falling edge of the 5$6 signal according to the DRAM connected and the operating
frequency of this LSI. Figure 6.24 shows an example of the timing when one T
Read
Write
Note: n = 2 to 5
Figure 6.24 Example of Timing with One Row Address Output Maintenance State
ø
Address bus
Data bus
Data bus
(
(
(
(
,
(
)
)
)
)
)
r
cycle, in which the 5$6 signal goes low, and the T
T
p
(RAST = 0, CAST = 0)
Row address
T
r
rw
states, in which row address output is maintained,
T
rw
Rev. 2.0, 04/02, page 177 of 906
High
High
T
Column address
c1
rw
c1
state is set.
cycle, in which
T
c2