HD6432670 Hitachi, HD6432670 Datasheet - Page 366

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

When the write data buffer function is activated, the DMAC recognizes that the bus cycle
concerned has ended, and starts the next operation. Therefore,
state after the start of the DMA write cycle or single address transfer.
7.5.12
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table
7.11 summarizes the priority order for DMAC channels.
Table 7.11 DMAC Channel Priority Order
Short Address Mode
Channel 0A
Channel 0B
Channel 1A
Channel 1B
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released, the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the
channel will not be changed until the end of the transfer. Figure 7.34 shows a transfer example in
which transfer requests are issued simultaneously for channels 0A, 0B, and 1.
Rev. 2.0, 04/02, page 320 of 906
Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function
Internal read signal
External address
Internal address
Multi-Channel Operation
ø
DMA
read
DMA
single
Full Address Mode
Channel 0
Channel 1
CPU
read
DMA
single
pin sampling is started one
Priority
High
Low
CPU
read