HD6432670 Hitachi, HD6432670 Datasheet - Page 190

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit
15
14
13
12
11
10
Rev. 2.0, 04/02, page 144 of 906
H8S/2678R Series
Bit Name
DRMI
TPC1
TPC0
SDWCD
—
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Idle Cycle Insertion
An idle cycle can be inserted after a
DRAM/synchronous DRAM access cycle when
a continuous normal space access cycle follows
a DRAM/synchronous DRAM access cycle. Idle
cycle insertion conditions, setting of number of
states, etc., comply with settings of bits ICIS2,
ICIS1, ICIS0, and IDLC in BCR register
0: Idle cycle not inserted
1: Idle cycle inserted
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
Precharge State Control
These bits select the number of states in the
RAS precharge cycle in normal access and
refreshing.
00: 1 state
01: 2 states
10: 3 states
11: 4 states
CAS Latency Control Cycle Disabled during
Continuous Synchronous DRAM Space Write
Access
Disables CAS latency control cycle (Tc1)
inserted by WTCR settings during synchronous
DRAM write access (see figure 6.5).
0: Enables CAS latency control cycle
1: Disables CAS latency control cycle
Reserved
This bit can be read from or written to. However,
the write value should always be 0.