HD6432670 Hitachi, HD6432670 Datasheet - Page 20

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HD6432670

Manufacturer Part Number
HD6432670
Description
(HD64F267x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
12.5 Usage Notes................................................................................................................. 597
Section 13 8-Bit Timers (TMR) ..................................................................... 599
13.1 Features ....................................................................................................................... 599
13.2 Input/Output Pins......................................................................................................... 601
13.3 Register Descriptions ................................................................................................... 601
13.4 Operation..................................................................................................................... 607
13.5 Operation Timing......................................................................................................... 608
13.6 Operation with Cascaded Connection ........................................................................... 611
13.7 Interrupts ..................................................................................................................... 612
13.8 Usage Notes................................................................................................................. 614
Section 14 Watchdog Timer .......................................................................... 621
14.1 Features ....................................................................................................................... 621
14.2 Input/Output Pin .......................................................................................................... 622
14.3 Register Descriptions ................................................................................................... 622
Rev. 2.0, 04/02, page xviii of xliv
12.4.8 Pulse Output Triggered by Input Capture ......................................................... 597
12.5.1 Module Stop Mode Setting .............................................................................. 597
12.5.2 Operation of Pulse Output Pins ........................................................................ 597
13.3.1 Timer Counter (TCNT).................................................................................... 601
13.3.2 Time Constant Register A (TCORA) ............................................................... 602
13.3.3 Time Constant Register B (TCORB)................................................................ 602
13.3.4 Timer Control Register (TCR) ........................................................................ 602
13.3.5 Timer Control/Status Register (TCSR)............................................................. 604
13.4.1 Pulse Output.................................................................................................... 607
13.5.1 TCNT Incrementation Timing.......................................................................... 608
13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs ................ 609
13.5.3 Timing of Timer Output when Compare-Match Occurs.................................... 609
13.5.4 Timing of Compare Match Clear...................................................................... 610
13.5.5 Timing of TCNT External Reset ...................................................................... 610
13.5.6 Timing of Overflow Flag (OVF) Setting .......................................................... 611
13.6.1 16-Bit Counter Mode....................................................................................... 611
13.6.2 Compare Match Count Mode ........................................................................... 612
13.7.1 Interrupt Sources and DTC Activation ............................................................. 612
13.7.2 A/D Converter Activation................................................................................ 613
13.8.1 Contention between TCNT Write and Clear ..................................................... 614
13.8.2 Contention between TCNT Write and Increment.............................................. 614
13.8.3 Contention between TCOR Write and Compare Match .................................... 615
13.8.4 Contention between Compare Matches A and B............................................... 616
13.8.5 Switching of Internal Clocks and TCNT Operation .......................................... 617
13.8.6 Mode Setting with Cascaded Connection ......................................................... 619
13.8.7 Interrupts in Module Stop Mode ...................................................................... 619

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