DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 182

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller
DMAC
When the DMAC receives an activation request, it requests the bus right from the bus arbiter. If
the DMAC is bus master and the refresh controller or an external bus master requests the bus, the
bus arbiter transfers the bus right from the DMAC to the bus master that requested the bus. The
bus right is transferred at the following times.
The bus right is transferred when the DMAC finishes transferring 1 byte or 1 word. A DMAC
transfer cycle consists of a read cycle and a write cycle. The bus right is not transferred between
the read cycle and the write cycle.
There is a priority order among the DMAC channels. For details see section 8.4.9, DMAC
Multiple-Channel Operation.
Refresh Controller
When a refresh cycle is requested, the refresh controller requests the bus right from the bus arbiter.
When the refresh cycle is completed, the refresh controller releases the bus. For details see section
7, Refresh Controller.
External Bus Master
When the BRLE bit is set to 1 in BRCR, the bus can be released to an external bus master. The
external bus master has highest priority, and requests the bus right from the bus arbiter by driving
the BREQ signal low. Once the external bus master gets the bus, it keeps the bus right until the
BREQ signal goes high. While the bus is released to an external bus master, the H8/3048B Group
holds the address bus and data bus control signals (AS, RD, HWR, and LWR) in the high-
: n = 7 to 0), and holds the BACK pin in
impedance state, holds the chip select signals high (CS
n
the low output state.
The bus arbiter samples the BREQ pin at the rise of the system clock ( ). If BREQ is low, the bus
is released to the external bus master at the appropriate opportunity. The BREQ signal should be
held low until the BACK signal goes low.
When the BREQ pin is high in two consecutive samples, the BACK signal is driven high to end
the bus-release cycle.
Rev. 3.00 Sep 27, 2006 page 154 of 872
REJ09B0325-0300