DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 395

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.4.3
The synchronization function enables two or more timer counters to be synchronized by writing
the same data to them simultaneously (synchronous preset). With appropriate TCR settings, two or
more timer counters can also be cleared simultaneously (synchronous clear). Synchronization
enables additional general registers to be associated with a single time base. Synchronization can
be selected for all channels (0 to 4).
Sample Setup Procedure for Synchronization
Figure 10.26 shows a sample procedure for setting up synchronization.
1.
2.
3.
4.
5.
Set the SYNC bits to 1 in TSNC for the channels to be synchronized.
When a value is written in TCNT in one of the synchronized channels, the same value is
simultaneously written in TCNT in the other channels (synchronized preset).
Set the CCLR1 or CCLR0 bit in TCR to have the counter cleared by compare match or input capture.
Set the CCLR1 and CCLR0 bits in TCR to have the counter cleared synchronously.
Set the STR bits in TSTR to 1 to start the synchronized counters.
Setup for synchronization
Select synchronization
Synchronous preset
Synchronous preset
Synchronization
Write to TCNT
Figure 10.26 Setup Procedure for Synchronization (Example)
1
2
Select counter clear source
synchronized to this
Synchronous clear
Counter clear
Start counter
Clearing
channel?
Yes
Section 10 16-Bit Integrated Timer Unit (ITU)
Rev. 3.00 Sep 27, 2006 page 367 of 872
3
5
No
Select counter clear source
Synchronous clear
Start counter
REJ09B0325-0300
4
5