DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 517

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for
receiving serial data and indicates the procedure to follow.
No
No
Read RDRF flag in SSR
Clear RE bit to 0 in SCR
RDRF flag to 0 in SSR
and FER flags in SSR
from RDR, and clear
Read ORER, PER,
Read receive data
Start receiving
PER
ORER = 1?
RDRF = 1?
receiving?
Finished
Initialize
Figure 13.7 Sample Flowchart for Receiving Serial Data (1)
End
FER
No
Yes
Yes
(continued on next page)
Yes
Error handling
5
1
2
4
3
1.
2, 3.
4.
5.
Section 13 Serial Communication Interface
SCI initialization: the receive data function of
the RxD pin is selected automatically.
detection: if a receive error occurs, read the
ORER, PER, and FER flags in SSR to identify
the error. After executing the necessary error
handling, clear the ORER, PER, and FER
flags all to 0. Receiving cannot resume if any
of the ORER, PER, and FER flags remains
set to 1. When a framing error occurs, the
RxD pin can be read to detect the break state.
SCI status check and receive data read: read
SSR, check that RDRF is set to 1, then read
receive data from RDR and clear the RDRF
flag to 0. Notification that the RDRF flag has
changed from 0 to 1 can also be given by the
RXI interrupt.
To continue receiving serial data: check the
RDRF flag, read RDR, and clear the RDRF
flag to 0 before the stop bit of the current
frame is received. If the DMAC is activated
by an RXI interrupt to read the RDR value,
the RDRF flag is cleared automatically.
Rev. 3.00 Sep 27, 2006 page 489 of 872
Receive error handling and break
REJ09B0325-0300