DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 539

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The receive margin in asynchronous mode can therefore be expressed as in equation (1).
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Usage of DMAC
To have the DMAC read RDR, be sure to select the SCI receive-data-full interrupt (RXI) as the
activation source with bits DTS2 to DTS0 in DTCR.
Internal
base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = (0.5
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L:
F:
D = 0.5, F = 0
M = {0.5 – 1/(2
= 46.875% ............................................................................................. (2)
Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
2N
1
0
)
16)}
8 clocks
Start bit
(L
0.5) F
100%
16 clocks
7
D
N
0.5
(1 + F)
15 0
Section 13 Serial Communication Interface
Rev. 3.00 Sep 27, 2006 page 511 of 872
100% ................... (1)
D
0
7
REJ09B0325-0300
15 0
D
1