DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 644

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
Notes on Using the Emulation Function by RAM
1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of
2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm
3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table
4. Flash write enable (FWE) application and releasing
5. Prohibited conditions of NMI input
18.10
The H8/3048F-ONE has a PROM mode as well as the on-board programming modes for
programming and erasing flash memory. In PROM mode, the on-chip ROM can be freely
programmed using a general-purpose PROM writer that supports the Renesas Technology
microcomputer device type with 128-kbyte on-chip flash memory.
Rev. 3.00 Sep 27, 2006 page 616 of 872
REJ09B0325-0300
the value of RAM2 and RAM1 (emulation protection). In this state, setting the P or E bit in
flash memory control register 1 (FLMCR1), will not cause a transition to program mode or
erase mode. When actually programming or erasing a flash memory area, the RAMS bit should
be cleared to 0.
while flash memory emulation in RAM is being used.
is needed by the overlap RAM.
As in on-board programming mode, care is required when applying and releasing FWE to
prevent erroneous programming or erasing. To prevent erroneous programming and erasing
due to program runaway during FWE application, in particular, the watchdog timer should be
set when the PSU, P, ESU, or E bit in FLMCR1 is set to 1, even while the emulation function
is being used. For details, see section 18.11, Notes on Flash Memory Programming/Erasing.
When the emulation function is used, NMI input is prohibited when the P bit or E bit in
FLMCR1 is set to 1, in the same way as with normal programming and erasing. The P and E
bits are cleared by a reset (including a watchdog timer reset), in standby mode, when a high
level is not being input to the FWE pin, or when the SWE bit in FLMCR1 is 0, while a high
level is being input to the FWE pin.
Flash Memory PROM Mode