DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 381

MCU 3/5V 128K PB-FREE 100-TQFP

DF3048BVX25V

Manufacturer Part Number
DF3048BVX25V
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3048BVX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3048BVX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the
OVF flag in TSR when OVF is set to 1.
Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the
interrupt requested by the IMFB flag in TSR when IMFB is set to 1.
Bit 0—Input Capture/Compare Match Interrupt Enable A (IMIEA): Enables or disables the
interrupt requested by the IMFA flag in TSR when IMFA is set to 1.
10.3
10.3.1
The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A
and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data
bus. These registers can be written or read a word at a time, or a byte at a time.
Figures 10.6 and 10.7 show examples of word access to a timer counter (TCNT). Figures 10.8 to
10.11 show examples of byte access to TCNTH and TCNTL.
Bit 2: OVIE
0
1
Bit 1: IMIEB
0
1
Bit 0: IMIEA
0
1
CPU Interface
16-Bit Accessible Registers
Description
OVI interrupt requested by OVF is disabled
OVI interrupt requested by OVF is enabled
Description
IMIB interrupt requested by IMFB is disabled
IMIB interrupt requested by IMFB is enabled
Description
IMIA interrupt requested by IMFA is disabled
IMIA interrupt requested by IMFA is enabled
Section 10 16-Bit Integrated Timer Unit (ITU)
Rev. 3.00 Sep 27, 2006 page 353 of 872
REJ09B0325-0300
(Initial value)
(Initial value)
(Initial value)

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