DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 339

MCU 3/5V 128K PB-FREE 100-TQFP

DF3048BVX25V

Manufacturer Part Number
DF3048BVX25V
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3048BVX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3048BVX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.12.2
Table 9.20 summarizes the registers of port B.
Table 9.20 Port B Registers
Address *
H'FFD4
H'FFD6
Note:
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that can select input or output for each pin in port B. When
pins are used for TPC output, the corresponding PBDDR bits must also be set.
While port B acts as an I/O port, a pin in port B becomes an output pin if the corresponding
PBDDR bit is set to 1, and an input pin if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. If a PBDDR bit is set to 1 while port B acts as an I/O port, the
corresponding pin maintains its output state in software standby mode.
Bit
Initial value
Read/Write
* Lower 16 bits of the address.
Register Descriptions
Name
Port B data direction register
Port B data register
PB DDR
7
W
7
0
PB DDR
6
W
6
0
PB DDR
5
W
5
0
Port B data direction 7 to 0
These bits select input or output for port B pins
PB DDR
4
W
4
0
PBDDR
PBDR
Abbreviation
PB DDR
Rev. 3.00 Sep 27, 2006 page 311 of 872
3
W
3
0
PB DDR
2
W
2
0
R/W
W
R/W
PB DDR
Section 9 I/O Ports
REJ09B0325-0300
1
W
1
0
Initial Value
H'00
H'00
PB DDR
0
W
0
0

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