DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 630

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
18.7.1
To write data or programs to flash memory, the program/program-verify flowchart shown in figure
18.13 should be followed. Performing program operations according to this flowchart will enable
data or programs to be written to flash memory without subjecting the device to voltage stress or
sacrificing program data reliability. Programming should be carried out 128 bytes at a time.
The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and
the maximum number of programming operations (N) are shown in table 21.11 in section 21.1.6,
Flash Memory Characteristics.
Following the elapse of (t
written consecutively to the write addresses. The lower 8 bits of the first address written to must
be H'00 and H'80, 128 consecutive byte data transfers are performed. The program address and
program data are latched in the flash memory. A 128-byte data transfer must be performed even if
writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
Set a value greater than (t
entering program mode (program setup) is performed next by setting the PSU bit in FLMCR1.
The operating mode is then switched to program mode by setting the P bit in FLMCR1 after the
elapse of at least (t
time. Make a program setting so that the time for one programming operation is within the range
of (t
The wait time after P bit setting must be changed according to the number of reprogramming
loops. For details, see Notes on Program/Program-Verify Procedure.
Rev. 3.00 Sep 27, 2006 page 602 of 872
REJ09B0325-0300
sp
) µs.
Program Mode
spsu
) µs. The time during which the P bit is set is the flash memory programming
sswe
spsu
) µs or more after the SWE bit is set to 1 in FLMCR1, 128-byte data is
+ t
sp
+ t
cp
+ t
cpsu
) µs as the WDT overflow period. Preparation for