DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 621

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.6.1
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The SCI channel to be used is set to asynchronous mode.
When a reset-start is executed after H8/3048F-ONE’s pins have been set to boot mode, the boot
program built into the LSI is started and the programming control program prepared in the host is
serially transmitted to the LSI via the SCI. In the LSI, the programming control program received
via the SCI is written into the programming control program area in on-chip RAM. After the
transfer is completed, the programming control program is recognized (the ID code is checked) if
it corresponds to the H8/3048F-ONE. When the ID code is matched, control branches to the start
address of the programming control program area and the programming control program execution
state is entered (flash memory programming is performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 18.7, and the boot mode execution
procedure in figure 18.8.
Note: * For pins RxD1 and TxD1, use on-board pull-up.
Boot Mode
Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
Host
Figure 18.7 System Configuration in Boot Mode
Verify data transmission
Write data reception
Rev. 3.00 Sep 27, 2006 page 593 of 872
RxD1 *
TxD1 *
SCI1
H8/3048F-ONE
Flash memory
On-chip RAM
REJ09B0325-0300