DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 893

MCU 3/5V 128K PB-FREE 100-TQFP

DF3048BVX25V

Manufacturer Part Number
DF3048BVX25V
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3048BVX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3048BVX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
D.2
Reset in T1 State
Figure D.1 is a timing diagram for the case in which RES goes low during the T1 state of an
external memory access cycle. As soon as RES goes low, all ports are initialized to the input state.
AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance state. The address
bus is initialized to the low output level 0.5 state after the low level of RES is sampled. Sampling
of RES takes place at the fall of the system clock ( ).
RES
Internal
reset signal
Address bus
CS
CS
AS
RD (read access)
HWR, LWR
(write access)
Data bus
(write access)
I/O port
0
7
Pin States at Reset
to CS
Figure D.1 Reset during Memory Access (Reset during T1 State)
1
High
High
High
Access to external address
T1
T2
Rev. 3.00 Sep 27, 2006 page 865 of 872
T3
H'000000
Appendix D Pin States
High-impedance
High-impedance
High-impedance
REJ09B0325-0300

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