DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 30

MCU 3/5V 128K PB-FREE 100-TQFP

DF3048BVX25V

Manufacturer Part Number
DF3048BVX25V
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3048BVX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3048BVX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 1 Overview
Table 1.1
Feature
CPU
Memory
Interrupt
controller
Bus controller
Rev. 3.00 Sep 27, 2006 page 2 of 872
REJ09B0325-0300
Features
Description
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
High-speed operation (flash memory version)
Instruction features
ROM: 128 kbytes
RAM: 4 kbytes
Seven external interrupt pins: NMI, IRQ
30 internal interrupts
Three selectable interrupt priority levels
Address space can be partitioned into eight areas, with independent bus
specifications in each area
Chip select output available for areas 0 to 7
8-bit access or 16-bit access selectable for each area
Two-state or three-state access selectable for each area
Selection of four wait modes
Bus arbitration function
Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers + eight 16-bit registers or eight 32-
bit registers)
Maximum clock rate: 25 MHz
Add/subtract: 80 ns
Multiply/divide: 560 ns
16-Mbyte address space
8/16/32-bit data transfer, arithmetic, and logic instructions
Signed and unsigned multiply instructions (8 bits
bits)
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16
bits)
Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit
positions
0
to IRQ
5
8 bits, 16 bits
16

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