DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 426

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 16-Bit Integrated Timer Unit (ITU)
10.5.2
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 10.60 shows the timing.
10.5.3
Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input
capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all
independently vectored. An interrupt is requested when the interrupt request flag and interrupt
enable bit are both set to 1.
The priority order of the channels can be modified in interrupt priority registers A and B (IPRA
and IPRB). For details see section 5, Interrupt Controller.
Compare match/input capture A interrupts in channels 0 to 3 can activate the DMA controller
(DMAC). When the DMAC is activated a CPU interrupt is not requested.
Table 10.10 lists the interrupt sources.
Rev. 3.00 Sep 27, 2006 page 398 of 872
REJ09B0325-0300
Address
IMF, OVF
Timing of Clearing of Status Flags
Interrupt Sources and DMA Controller Activation
Figure 10.60 Timing of Clearing of Status Flags
T
1
TSR write cycle
TSR address
T
2
T
3