DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 45

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Type
Bus control
Refresh
controller
Symbol
CS
AS
RD
HWR
LWR
WAIT
RFSH
CS
RD
HWR
LWR
7
3
to CS
0
Pin No.
8, 97 to 99,
88 to 91
69
70
71
72
58
87
88
70
71
72
I/O
Output
Output
Output
Output
Output
Input
Output
Output
Output
Output
Output
Name and Function
Chip select: Select signals for areas 7 to 0
Address strobe: Goes low to indicate valid
address output on the address bus
Read: Goes low to indicate reading from
the external address space
High write: Goes low to indicate writing to
the external address space; indicates valid
data on the upper data bus (D
Low write: Goes low to indicate writing to
the external address space; indicates valid
data on the lower data bus (D
Wait: Requests insertion of wait states in
bus cycles during access to the external
address space
Refresh: Indicates a refresh cycle
Row address strobe RAS
strobe signal for DRAM connected to area 3
Column address strobe CAS
address strobe signal for DRAM connected
to area 3; used with 2WE DRAM.
Write enable WE
DRAM connected to area 3; used with
2CAS DRAM.
Upper write UW
DRAM connected to area 3; used with 2WE
DRAM.
Upper column address strobe UCAS
Column address strobe signal for DRAM
connected to area 3; used with 2CAS
DRAM.
Lower write LW
DRAM connected to area 3; used with 2WE
DRAM.
Lower column address strobe LCAS
Column address strobe signal for DRAM
connected to area 3; used with 2CAS
DRAM.
Rev. 3.00 Sep 27, 2006 page 17 of 872
UW: Write enable signal for
UW
UW
LW: Write enable signal for
LW
LW
WE: Write enable signal for
WE
WE
RAS
RAS: Row address
RAS
Section 1 Overview
REJ09B0325-0300
CAS
CAS: Column
CAS
7
15
to D
to D
UCAS
UCAS:
UCAS
LCAS:
LCAS
LCAS
0
).
8
).