DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 474

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Watchdog Timer
12.2.3
RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip
internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to
initialize external system devices. Note that there is no RESO pin in the versions with on-chip
flash memory.
Bit 7
WRST
0
1
Rev. 3.00 Sep 27, 2006 page 446 of 872
REJ09B0325-0300
Bit
Initial value
Read/Write
Notes: The method for writing to RSTCSR is different from that for general registers to prevent
Reset Control/Status Register (RSTCSR)
inadvertent overwriting. For details see section 12.2.4, Notes on Register Rewriting.
* Only 0 can be written in bit 7, to clear the flag.
Watchdog timer reset
Indicates that a reset signal has been generated
Description
[Clearing conditions]
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
R/(W)
WRST
Reset signal at RES pin.
Read WRST when WRST = 1, then write 0 in WRST.
7
0
*
Reset output enable
Enables or disables external output of the reset signal
RSTOE
R/W
6
0
5
1
4
1
Reserved bits
3
1
2
1
1
1
(Initial value)
0
1