DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 519

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

In receiving, the SCI operates as follows.
1. The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes
2. Receive data is stored in RSR in order from LSB to MSB.
3. The parity bit and stop bit are received.
Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag
4. When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
Table 13.11 Receive Error Conditions
Receive Error
Overrun error
Framing error
Parity error
internally and starts receiving.
After receiving, the SCI makes the following checks:
a. Parity check: The number of 1s in the receive data must match the even or odd parity
b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit
c. Status check: The RDRF flag must be 0 so that receive data can be transferred from RSR
If these checks all pass, the RDRF flag is set to 1 and the received data is stored in RDR. If one
of the checks fails (receive error) * , the SCI operates as indicated in table 13.11.
(RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also
set to 1, a receive-error interrupt (ERI) is requested.
setting of the O/E bit in SMR.
is checked.
into RDR.
is not set to 1. Be sure to clear the error flags to 0.
Abbreviation
ORER
FER
PER
Condition
while RDRF flag is still set
to 1 in SSR
Stop bit is 0
from even/odd parity setting
in SMR
Receiving of next data ends
Parity of receive data differs
Section 13 Serial Communication Interface
Rev. 3.00 Sep 27, 2006 page 491 of 872
Receive data not transferred
from RSR to RDR
Receive data transferred from
RSR to RDR
Receive data transferred from
RSR to RDR
Data Transfer
REJ09B0325-0300