HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 13

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.3
10.4
10.5
10.6
Section 11
11.1
11.2
11.3
10.2.11 Timer I/O Control Register (TIOR)................................................................ 310
10.2.12 Timer Status Register (TSR)........................................................................... 312
10.2.13 Timer Interrupt Enable Register (TIER)......................................................... 315
CPU Interface ................................................................................................................. 317
10.3.1
10.3.2
Operation ........................................................................................................................ 321
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.4.8
10.4.9
Interrupts ........................................................................................................................ 362
10.5.1
10.5.2
10.5.3
Usage Notes .................................................................................................................... 366
Overview ........................................................................................................................ 381
11.1.1
11.1.2
11.1.3
11.1.4
Register Descriptions...................................................................................................... 385
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.2.7
11.2.8
11.2.9
11.2.10 TPC Output Mode Register (TPMR).............................................................. 396
Operation ........................................................................................................................ 398
11.3.1
16-Bit Accessible Registers ............................................................................ 317
8-Bit Accessible Registers .............................................................................. 319
Overview......................................................................................................... 321
Basic Functions............................................................................................... 322
Synchronization .............................................................................................. 332
PWM Mode .................................................................................................... 334
Reset-Synchronized PWM Mode ................................................................... 338
Complementary PWM Mode.......................................................................... 341
Phase Counting Mode..................................................................................... 351
Buffering......................................................................................................... 353
ITU Output Timing......................................................................................... 360
Setting of Status Flags .................................................................................... 362
Clearing of Status Flags.................................................................................. 364
Interrupt Sources and DMA Controller Activation ........................................ 365
Programmable Timing Pattern Controller
Features........................................................................................................... 381
Block Diagram................................................................................................ 382
TPC Pins ......................................................................................................... 383
Registers ......................................................................................................... 384
Port A Data Direction Register (PADDR) ...................................................... 385
Port A Data Register (PADR) ......................................................................... 385
Port B Data Direction Register (PBDDR) ...................................................... 386
Port B Data Register (PBDR) ......................................................................... 386
Next Data Register A (NDRA)....................................................................... 387
Next Data Register B (NDRB) ....................................................................... 389
Next Data Enable Register A (NDERA) ........................................................ 391
Next Data Enable Register B (NDERB)......................................................... 392
TPC Output Control Register (TPCR)............................................................ 393
Overview......................................................................................................... 398
......................................... 381