HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 206

MCU 5V 0K PB-FREE 112-QFP

HD6413003TF16V

Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413003TF16V

Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
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ITT
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Part Number:
HD6413003TF16V
Manufacturer:
RENESAS
Quantity:
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Part Number:
HD6413003TF16V
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Channel B
Bit 2
DTS2B
0
1
Note: * DMAC channels 0 and 1 accept transmit-data-empty and receive-data-full interrupts from
The same internal interrupt can be selected as an activation source for two or more channels at
once. In that case the channels are activated in a priority order, highest-priority channel first. For
the priority order, see section 8.4.9, Multiple-Channel Operation.
When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a
CPU interrupt.
SCI channel 0. DMAC channels 2 and 3 accept transmit-data-empty and receive-data-full
interrupts from SCI channel 1.
Bit 1
DTS1B
0
1
0
1
Bit 0
DTS0B
0
1
0
1
0
1
0
1
Description
Compare match/input capture A interrupt from ITU
channel 0
Compare match/input capture A interrupt from ITU channel 1
Compare match/input capture A interrupt from ITU channel 2
Compare match/input capture A interrupt from ITU channel 3
Transmit-data-empty interrupt from SCI channel 0 or 1*
Receive-data-full interrupt from SCI channel 0 or 1*
Falling edge of DREQ input
Low level of DREQ input
186
(Initial value)

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