HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 22

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1-1 Features (cont)
Feature
Memory
Interrupt
controller
Bus controller
Refresh
controller
DMA controller
(DMAC)
Description
RAM: 512 bytes
• Nine external interrupt pins: NMI, IRQ
• 34 internal interrupts
• Three selectable interrupt priority levels
• Address space can be partitioned into eight areas, with independent bus
• Chip select output available for each area
• 8-bit access or 16-bit access selectable for each area
• Two-state or three-state access selectable for each area
• Selection of four wait modes
• Bus arbitration function
DRAM refresh
• Directly connectable to 16-bit-wide DRAM
• CAS-before-RAS refresh
• Self-refresh mode selectable
Pseudo-static RAM refresh
• Self-refresh mode selectable
Usable as an interval timer
Short address mode
• Maximum eight channels available
• Selection of I/O mode, idle mode, or repeat mode
• Can be activated by compare match/input capture A interrupts from ITU
Full address mode
• Maximum four channels available
• Selection of normal mode or block transfer mode
• Can be activated by compare match/input capture A interrupts from ITU
specifications in each area
channels 0 to 3, SCI transmit-data-empty and receive-data-full interrupts, or
external requests
channels 0 to 3, external requests, or auto-request
2
0
to IRQ
7