HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 155

MCU 5V 0K PB-FREE 112-QFP

HD6413003TF16V

Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413003TF16V

Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Quantity
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7.1 Overview
The H8/3003 has an on-chip refresh controller that enables direct connection of 16-bit-wide
DRAM or pseudo-static RAM (PSRAM).
DRAM or pseudo-static RAM can be directly connected to area 3 of the external address space.
A maximum 128 kbytes can be connected in modes 1 and 2 (1-Mbyte modes). A maximum
2 Mbytes can be connected in modes 3 and 4 (16-Mbyte modes).
Systems that do not need to refresh DRAM or pseudo-static RAM can use the refresh controller as
an 8-bit interval timer.
7.1.1 Features
The refresh controller can be used for one of three functions: DRAM refresh control, pseudo-static
RAM refresh control, or 8-bit interval timing. Features of the refresh controller are listed below.
Features as a DRAM Refresh Controller
Features as a Pseudo-Static RAM Refresh Controller
Enables direct connection of 16-bit-wide DRAM
Selection of 2CAS or 2WE mode
Selection of 8-bit or 9-bit column address multiplexing for DRAM address input
Examples:
— 1-Mbit DRAM: 8-bit row address 8-bit column address
— 4-Mbit DRAM: 9-bit row address 9-bit column address
— 4-Mbit DRAM: 10-bit row address 8-bit column address
CAS-before-RAS refresh control
Software-selectable refresh interval
Software-selectable self-refresh mode
Wait states can be inserted
RFSH signal output for refresh control
Software-selectable refresh interval
Software-selectable self-refresh mode
Wait states can be inserted
Section 7 Refresh Controller
135

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