HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 599

MCU 5V 0K PB-FREE 112-QFP

HD6413003TF16V

Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413003TF16V

Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6413003TF16V
Manufacturer:
ITT
Quantity:
12 000
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS
Quantity:
36
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Table A-3 Number of Cycles per Instruction (cont)
Instruction Mnemonic
RTS
SHAL
SHAR
SHLL
SHLR
SLEEP
STC
SUB
SUBS
SUBX
TRAPA
XOR
XORC
Notes: 1. n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each.
2. For the number of states required for data access, refer to the relevant hardware manual.
3. Not available in the H8/3003.
RTS
SHAL.B Rd
SHAL.W Rd
SHAL.L ERd
SHAR.B Rd
SHAR.W Rd
SHAR.L ERd
SHLL.B Rd
SHLL.W Rd
SHLL.L ERd
SHLR.B Rd
SHLR.W Rd
SHLR.L ERd
SLEEP
STC CCR, Rd
STC CCR, @ERd
STC CCR, @(d:16, ERd) 3
STC CCR, @(d:24, ERd) 5
STC CCR, @–ERd
STC CCR, @aa:16
STC CCR, @aa:24
SUB.B Rs, Rd
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
SUBS #1/2/4, ERd
SUBX #xx:8, Rd
SUBX Rs, Rd
TRAPA #x:2 Normal
XOR.B #xx:8, Rd
XOR.B Rs, Rd
XOR.W #xx:16, Rd
XOR.W Rs, Rd
XOR.L #xx:32, ERd
XOR.L ERs, ERd
XORC #xx:8, CCR
Normal
Advanced 2
Advanced 2
*1
*1
Instruction Branch
Fetch
I
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
4
1
2
1
3
1
1
1
1
2
1
1
2
1
3
2
1
Addr. Read Operation Access
J
1
2
579
Stack
K
1
2
2
2
Byte Data Word Data Internal
L
Access
M
1
1
1
1
1
1
N
2
2
2
4
4
Operation

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