HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 19

MCU 5V 0K PB-FREE 112-QFP

HD6413003TF16V

Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413003TF16V

Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6413003TF16V
Manufacturer:
ITT
Quantity:
12 000
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS
Quantity:
36
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Page
P514
P529 to Table 18-4
P536
P520 to Table 18-2
P526
P529 to Table 18-4
P531
P532
P536
P541
P543
P545
P555
P556
P557
P566
P575
P673
Item
17.3.2
Table 18-5
Table 18-8
Figure 18-7
Figure 18-10 DRAM Bus Timing (Read/Write):
Figure 18-13 PSRAM Bus Timing (Read/Write):
Table A-1
Table A-1
Table A-1
Table A-1
Table A-1
Table A-1
Table A-1
Table A-1
Table A-3
Figure C-4
to 18-8
Exit from Sleep Mode
Exit by Interrupt
Electrical Characteristics
DC Characteristics
Bus Timing
Refresh Controller Bus Timing
A/D Conversion Characteristics
DRAM Bus Timing (Read/Write):
Three-State Access
— 2WE Mode —
Three-State Access
— 2CAS Mode —
Three-State Access
Instruction Set
MOV. B Rs, @(d:16, ERd)
Instruction Set
MOV. B Rs, @(d:24, ERd)
Instruction Set
MOV. W Rs, @(d:16, ERd)
Instruction Set
MOV. W Rs, @(d:24, ERd)
Instruction Set MOV. L #xx:32, Rd Number of execution states amended
Instruction Set POP, L ERn
Instruction Set PUSH. L ERn
Instruction Set STC
Number of Cycles per Instruction
BSRd:16
Port 7 Block Diagram (Pin P7n)
Description
Description amended
Condition values amended
Values changed and added to table
Values changed
Values changed
Values changed
*added
*added
*added
Operation amended
Operation amended
Operation amended
Operation and number of execution
states amended
Number of execution states amended
Number of execution states amended
Menmonics amended (3 places)
Internal operation added
Figure amended

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