HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 250

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.5 Interrupts
The DMAC generates only DMA-end interrupts. Table 8-13 lists the interrupts and their priority.
Table 8-13 DMAC Interrupts
Group
0
1
Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control
register (DTCR). Separate interrupt signals are sent to the interrupt controller.
The interrupt priority order among channels is channel 0 > channel 1 > channel 2 > channel 3, and
channel A > channel B. The interrupt priority order between groups can be modified in interrupt
priority register B (IPRB).
Figure 8-26 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and
DTIE = 1.
DEND0A
DEND0B
DEND1A
DEND1B
DEND2A
DEND2B
DEND3A
DEND3B
Interrupt
Short Address Mode
End of transfer on channel 0A
End of transfer on channel 0B
End of transfer on channel 1A
End of transfer on channel 1B
End of transfer on channel 2A
End of transfer on channel 2B
End of transfer on channel 3A
End of transfer on channel 3B
Description
230
Full Address Mode
End of transfer on
channel 0
—
End of transfer on
channel 1
—
End of transfer on
channel 2
—
End of transfer on
channel 3
—
High
Low
Interrupt Priority