HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 255

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8-14 Address Ranges Specifiable in MAR and IOAR
MAR
IOAR
MAR bits 23 to 20 are ignored in 1-Mbyte mode.
8.6.8 Bus Cycle when Transfer is Aborted
When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME
bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead
cycle occurs. This dead cycle does not update the halted channel’s address register or counter
value. Figure 8-28 shows an example in which an auto-requested transfer in cycle-steal mode on
channel 0 is aborted by clearing the DTE bit in channel 0.
ø
Address bus
RD
GW, LWR
Figure 8-28 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode
1-Mbyte Mode
H'00000 to H'FFFFF
(0 to 1048575)
H'FFF00 to H'FFFFF
(1048320 to 1048575)
CPU cycle
T
1
T
2
T
d
T
1
DMAC cycle
T
2
16-Mbyte Mode
H'000000 to H'FFFFFF
(0 to 16777215)
(16776960 to 16777215)
H'FFFF00 to H'FFFFFF
T
1
235
T
2
T
1
CPU cycle
DTE bit is
cleared
T
2
T
3
T
d
DMAC
cycle
T
d
T
1
CPU cycle
T
2