HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 216

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4 Operation
8.4.1 Overview
Table 8-5 summarizes the DMAC modes.
Table 8-5 DMAC Modes
Transfer Mode
Short address
mode
Full address
mode
A summary of operations in these modes follows.
I/O Mode: One byte or word is transferred per request. A designated number of these transfers
are executed. A CPU interrupt can be requested at completion of the designated number of
transfers. One 24-bit address and one 8-bit address are specified. The transfer direction is
determined automatically from the activation source.
Idle Mode: One byte or word is transferred per request. A designated number of these transfers
are executed. A CPU interrupt can be requested at completion of the designated number of
transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed. The
transfer direction is determined automatically from the activation source.
Repeat Mode: One byte or word is transferred per request. A designated number of these
transfers are executed. When the designated number of transfers are completed, the initial address
and counter value are restored and operation continues. No CPU interrupt is requested. One 24-bit
address and one 8-bit address are specified. The transfer direction is determined automatically
from the activation source.
Activation
Normal mode
Block transfer mode
I/O mode
Idle mode
Repeat mode
Notes
Compare match/input
capture A interrupt from
ITU channels 0 to 3
SCI transmit-data-empty
and receive-data-full
interrupts
External request
Auto-request
External request
Compare match/input
capture A interrupt from
ITU channels 0 to 3
External request
196
• Up to eight channels
• Only the B channels
• A and B channels are
• Burst mode or cycle-
can operate
independently
support external
requests
paired; up to four
channels are
available
steal mode can be
selected for auto-
requests