HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 320

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bits 5 and 4—Combination Mode 1 and 0 (CMD1, CMD0): These bits select whether channels
3 and 4 operate in normal mode, complementary PWM mode, or reset-synchronized PWM mode.
Bit 5
CMD1
0
1
Before selecting reset-synchronized PWM mode or complementary PWM mode, halt the timer
counter or counters that will be used in these modes.
When these bits select complementary PWM mode or reset-synchronized PWM mode, they take
precedence over the setting of the PWM mode bits (PWM4 and PWM3) in TMDR. Settings of
timer sync bits SYNC4 and SYNC3 in the timer synchro register (TSNC) are valid in
complementary PWM mode and reset-synchronized PWM mode, however. When complementary
PWM mode is selected, channels 3 and 4 must not be synchronized (do not set bits SYNC3 and
SYNC4 both to 1 in TSNC).
Bit 3—Buffer Mode B4 (BFB4): Selects whether GRB4 operates normally in channel 4, or
whether GRB4 is buffered by BRB4.
Bit 3
BFB4
0
1
Bit 2—Buffer Mode A4 (BFA4): Selects whether GRA4 operates normally in channel 4, or
whether GRA4 is buffered by BRA4.
Bit 2
BFA4
0
1
Bit 4
CMD0
0
1
0
1
Description
GRB4 operates normally
GRB4 is buffered by BRB4
Description
GRA4 operates normally
GRA4 is buffered by BRA4
Description
Channels 3 and 4 operate normally
Channels 3 and 4 operate together in complementary PWM mode
Channels 3 and 4 operate together in reset-synchronized PWM mode
300
(Initial value)
(Initial value)
(Initial value)