HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 218

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.2 I/O Mode
I/O mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in I/O mode. A designated number of
these transfers are executed. One address is specified in the memory address register (MAR), the
other in the I/O address register (IOAR). The direction of transfer is determined automatically
from the activation source. The transfer is from the address specified in IOAR to the address
specified in MAR if activated by an SCI receive-data-full interrupt, and from the address specified
in MAR to the address specified in IOAR otherwise.
Table 8-6 indicates the register functions in I/O mode.
Table 8-6 Register Functions in I/O Mode
Register
Legend
MAR:
IOAR: I/O address register
ETCR: Execute transfer count register
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address, which is incremented or decremented as each byte or word is transferred.
IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not
incremented or decremented.
Figure 8-2 illustrates how I/O mode operates.
23
23
All 1s
Memory address register
15
MAR
ETCR
7
IOAR
0
0
0
Activated by
SCI Receive-
Data-Full
Interrupt
Destination
address
register
Source
address
register
Transfer counterNumber of
Function
198
Other
Activation
Source
address
register
Destination
address
register
Initial Setting
Destination or
source address
Source or
destination
address
Decremented
transfers
Operation
Incremented or
decremented
once per transfer
Held fixed
once per
transfer until
H'0000 is
reached and
transfer ends