HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 302

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

•
•
•
•
•
•
— PWM mode
Phase counting mode selectable in channel 2
Two-phase encoder output can be counted automatically.
Three additional modes selectable in channels 3 and 4
— Reset-synchronized PWM mode
— Complementary PWM mode
— Buffering
High-speed access via internal 16-bit bus
The 16-bit timer counters, general registers, and buffer registers can be accessed at high speed
via a 16-bit bus.
Fifteen interrupt sources
Each channel has two compare match/input capture interrupts and an overflow interrupt. All
interrupts can be requested independently.
Activation of DMA controller (DMAC)
Four of the compare match/input capture interrupts from channels 0 to 3 can start the DMAC.
Output triggering of programmable pattern controller (TPC)
Compare match/input capture signals from channels 0 to 3 can be used as TPC output
triggers.
PWM output can be provided with an arbitrary duty cycle. With synchronization, up to
five-phase PWM output is possible
If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of
complementary waveforms.
If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of
non-overlapping complementary waveforms.
Input capture registers can be double-buffered. Output compare registers can be updated
automatically.
282