HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 367

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when an
underflow occurs. When buffering is selected, buffer register contents are transferred to the
general register at compare match A3 during up-counting, and when TCNT4 underflows.
General Register Settings in Complementary PWM Mode: When setting up general registers
for complementary PWM mode or changing their settings during operation, note the following
points.
•
•
•
Initial settings
Do not set values from H'0000 to T – 1 (where T is the initial value of TCNT3). After the
counters start and the first compare match A3 event has occurred, however, settings in this
range also become possible.
Changing settings
Use the buffer registers. Correct waveform output may not be obtained if a general register is
written to directly.
Cautions on changes of general register settings
Figure 10-39 shows six correct examples and one incorrect example.
Buffer transfer
signal (BR to GR)
TCNT4
OVF
GR
Figure 10-38 Undershoot Timing
H'0001
H'0000
347
Buffer transfer
Set to 1
Underflow
H'FFFF
Overflow
H'0000
Flag not set
No buffer transfer