SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 110
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SI4431-A0-FM
Manufacturer Part Number
SI4431-A0-FM
Description
IC TXRX ISM 930MHZ 3.6V 20-QFN
Manufacturer
Silicon Laboratories Inc
Specifications of SI4431-A0-FM
Package / Case
20-QFN
Mfg Application Notes
Transitioning SI4430/31 to Rev B
Frequency
240MHz ~ 930MHz
Data Rate - Maximum
128kbps
Modulation Or Protocol
FSK, GFSK, OOK
Power - Output
13dBm
Sensitivity
-118dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
18.5mA
Current - Transmitting
28mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Number Of Receivers
2
Number Of Transmitters
1
Wireless Frequency
240 MHz to 930 MHz
Output Power
13 dBm
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
28 mA
Minimum Operating Temperature
- 40 C
Modulation
FSK, GFSK, OOK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1633-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI4431-A0-FMR
Manufacturer:
SILICON
Quantity:
3 500
Part Number:
SI4431-A0-FMR
Manufacturer:
SILICONLABS/芯科
Quantity:
20 000
Register 23h. Clock Recovery Offset 0
Register 24h. Clock Recovery Timing Loop Gain 1
Register 25h. Clock Recovery Timing Loop Gain 0
Si4431
Reset value = 10101110
Reset value = 00000010
The loop gain can be calculated as follows:
Reset value = 10001111
110
Name
Name
Name
Type
Type
Type
Bit
Bit
Bit
7:0
7:3
2:0
7:0
Bit
Bit
Bit
crgain[10:8]
crgain[7:0]
Reserved
ncoff[7:0]
Name
Name
Name
D7
D7
D7
NCO Offset.
See formula above
Reserved.
Clock Recovery Timing Loop Gain.
Clock Recovery Timing Loop Gain.
D6
D6
D6
crgain
Reserved
R/W
D5
D5
D5
=
2
Preliminary Rev. 0.4
+
2
----------------------------------------------------------------------- -
15
D4
D4
D4
crgain[7:0]
ncoff[7:0]
1
rxosr
+
R/W
R/W
enmanch
Function
Function
Function
Fd
D3
D3
D3
Rb
D2
D2
D2
crgain[10:8]
R/W
D1
D1
D1
D0
D0
D0