SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 153

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

Register 7Bh. Turn Around and 15.4 Length Compliance
Register 7Ch. TX FIFO Control 1
Reset value = 01111011
Reset value = 00110111
Name
Name
Type
Type
Bit
Bit
6:3
1:0
7:6
5:0
Bit
Bit
7
2
15.4 Length
turn_around_en Turn Around Enable.
Reserved[6:3]
txafthr[5:0]
15.4 Length
Reserved
phase[1:0]
R/W
D7
Name
D7
Name
Reserved
R/W
Reserved.
TX FIFO Almost Full Threshold.
D6
D6
15.4 Packet Length Compliance.
If set, then PK Length definition for both TX and RX will also include the CRC bytes, If
reset, then the Length refers ONLY to the DATA payload. For example, writing “9” to
this register when it is set, means we are sending/expecting “7” bytes of DATA, and the
other “2” should be the CRC (CRC should be enabled separately).
Reserved.
Enabling for the turn around functionality.
Turn Around Phase.
The RX to TX and vice-versa change in frequency will happen (if bit [2] is set) at the last
byte, and these two registers set the bit position in which the frequency shifts should
occur. Make sure it does not happen to early otherwise the last bits will be missed.
D5
Reserved[6:3]
D5
R/W
Preliminary Rev. 0.4
D4
D4
D3
Function
Function
D3
txafthr[5:0]
turn_around_en
R/W
R/W
D2
D2
D1
D1
phase[1:0]
Si4431
R/W
D0
D0
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