SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 89
![IC TXRX ISM 930MHZ 3.6V 20-QFN](/photos/14/23/142339/si4431-a0-fm_sml.jpg)
SI4431-A0-FM
Manufacturer Part Number
SI4431-A0-FM
Description
IC TXRX ISM 930MHZ 3.6V 20-QFN
Manufacturer
Silicon Laboratories Inc
Specifications of SI4431-A0-FM
Package / Case
20-QFN
Mfg Application Notes
Transitioning SI4430/31 to Rev B
Frequency
240MHz ~ 930MHz
Data Rate - Maximum
128kbps
Modulation Or Protocol
FSK, GFSK, OOK
Power - Output
13dBm
Sensitivity
-118dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
18.5mA
Current - Transmitting
28mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Number Of Receivers
2
Number Of Transmitters
1
Wireless Frequency
240 MHz to 930 MHz
Output Power
13 dBm
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
28 mA
Minimum Operating Temperature
- 40 C
Modulation
FSK, GFSK, OOK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1633-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI4431-A0-FMR
Manufacturer:
SILICON
Quantity:
3 500
Part Number:
SI4431-A0-FMR
Manufacturer:
SILICONLABS/芯科
Quantity:
20 000
Register 05h. Interrupt Enable 1
Reset value = 00000000
Name
Type
Bit
Bit
7
6
5
4
3
2
1
0
encrcerror
entxffaem
entxffafull
enrxffafull
enpkvalid
enpksent
enfferr
R/W
enfferr
Name
D7
enext
entxffafull
Enable FIFO Underflow/Overflow.
When set to 1 the FIFO Underflow/Overflow interrupt will be enabled.
Enable TX FIFO Almost Full.
When set to 1 the TX FIFO Almost Full interrupt will be enabled.
Enable TX FIFO Almost Empty.
When set to 1 the TX FIFO Almost Empty interrupt will be enabled.
Enable RX FIFO Almost Full.
When set to 1 the RX FIFO Almost Full interrupt will be enabled.
Enable External Interrupt.
When set to 1 the External Interrupt will be enabled.
Enable Packet Sent.
When ipksent =1 the Packet Sense Interrupt will be enabled.
Enable Valid Packet Received.
When ipkvalid = 1 the Valid Packet Received Interrupt will be enabled.
Enable CRC Error.
When set to 1 the CRC Error interrupt will be enabled.
R/W
D6
entxffaem
R/W
D5
Preliminary Rev. 0.4
enrxffafull
R/W
D4
Function
enext
R/W
D3
enpksent
R/W
D2
enpkvalid
R/W
D1
Si4431
encrcerror
R/W
D0
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