SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 115

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

Register 30h. Data Access Control
Reset value = 10001101
Name
Type
Bit
1:0
Bit
7
6
5
4
3
2
enpacrx
Reserved
crcdonly
enpacrx
enpactx
crc[1:0]
R/W
Name
lsbfrst
D7
encrc
Enable Packet RX Handling.
If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled.
Setting enpacrx = 1 will enable automatic packet handling in the RX path. Register
30–4D allow for various configurations of the packet structure. Setting enpacrx = 0 will
not do any packet handling in the RX path. It will only receive everything after the sync
word and fill up the RX FIFO.
LSB First Enable.
The LSB of the data will be transmitted/received first if this bit is set.
CRC Data Only Enable.
When this bit is set to 1 the CRC is calculated on and checked against the packet data
fields only.
Reserved.
Enable Packet TX Handling.
If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled.
Setting enpactx = 1 will enable automatic packet handling in the TX path. Register 30–4D
allow for various configurations of the packet structure. Setting enpactx = 0 will not do
any packet handling in the TX path. It will only transmit what is loaded to the FIFO.
CRC Enable.
Cyclic Redundancy Check generation is enabled if this bit is set.
CRC Polynomial Selection.
00:
01:
10:
11:
lsbfrst
R/W
D6
CCITT
CRC-16 (IBM)
IEC-16
Biacheva
crcdonly
R/W
D5
Preliminary Rev. 0.4
Reserved
R/W
D4
enpactx
Function
R/W
D3
encrc
R/W
D2
D1
crc[1:0]
Si4431
R/W
D0
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