SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 24

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

Si4431
3.3. Interrupts
The Si4431 is capable of generating an interrupt signal when certain events occur. The chip notifies the
microcontroller that an interrupt event has been detected by setting the nIRQ output pin LOW = 0. This interrupt
signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits)
shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s)
(Registers 03h–04h) containing the active Interrupt Status bit; the nIRQ output signal will then be reset until the
next change in status is detected. All of the interrupts must be enabled by the corresponding enable bit in the
Interrupt Enable Registers (Registers 05h–06h). All enabled interrupt bits will be cleared when the microcontroller
reads the interrupt status register. If the interrupt is not enabled when the event occurs inside of the chip it will not
trigger the nIRQ pin, but the status may still be read correctly at anytime in the Interrupt Status registers.
Add R/W Function/Descript
See “Register 03h. Interrupt/Status 1,” on page 85 and “Register 04h. Interrupt/Status 2,” on page 87 for a
complete list of interrupts.
3.4. Device Code
The device version code is readable from "Register 01h. Version Code (VC)". This is a read only register.
24
Add R/W Function/Description
03
04
05 R/W
06 R/W
01
R
R
R
Interrupt Enable 1
Interrupt Enable 2
Interrupt Status 1
Interrupt Status 2
Device Version
ion
enswdet enpreaval enpreainval
enfferr
iswdet
ifferr
D7
D7
0
entxffafull entxffaem enrxffafull enext enpksent enpkvalid encrcerror
ipreaval
itxffafull
D6
D6
0
Preliminary Rev. 0.4
ipreainval
itxffaem
D5
D5
0
vc[4]
D4
irxffafull
enrssi
irssi
D4
vc[3]
D3
enwut
iwut
iext
D3
vc[2]
D2
ipksent
enlbd
ilbd
D2
vc[1]
D1
enchiprdy
ichiprdy
ipkvalid
D1
vc[0]
D0
icrcerror
enpor
POR Def. Notes
ipor
D0
00h
POR Def.
00h
01h
—
—
DV